1. Technical Field
The present invention relates to integrated circuits, and in particular to the tests conducted at the end of manufacturing an integrated circuit.
2. Description of the Related Art
These tests are generally conducted using a test machine which applies probes to the contact pads of the integrated circuit. The probes are in the form of needles having a distal end diameter in the order of a few micrometers. The integrated circuits are tested one after the other by moving the semi-conductive wafer onto which the integrated circuits are collectively implanted under a head supporting the probes. When the wafer is motionless, the head is moved vertically to apply the probes to the contact pads of an integrated circuit, then removed from the wafer when the latter is moved. The probes should be positioned on the contact pads of the integrated circuits very accurately, otherwise the integrated circuit could be damaged.
FIGS. 1 and 2 represent in perspective a contact pad Pa of an integrated circuit IC to which a probe PB is applied. The contact pad comprises an electrically conductive upper layer 1. The integrated circuit IC is furthermore covered by a passivating layer 2 in an electrically insulating material, such as a polymer or a glass, also covering the edges of the contact pads.
The tip of the probe PB which is applied to the contact pad Pa is tilted in relation to an axis perpendicular to the contact pad Pa. The result is that when the probe is lowered to be in contact with the contact pad, it bends slightly when the downward movement of the probe continues once it is in contact with the contact pad. Sufficient contact pressure is thus obtained. However, as the proximal end of the probe is fixed, the tip of the probe brushes a certain surface area of the contact pad Pa during the downward movement of the head once the probe is in contact with the contact pad.
The result is that, as shown in FIG. 2, if the tip of the probe PB comes into contact with the contact pad Pa near an edge thereof, the tip of the probe will tend to partially tear the passivating layer 2 off. The same is true if the downward travel of the probe PB is excessive. The tip of the probe then brushes a larger surface area of the contact pad with excessive pressure, which could damage the actual contact pad by crushing or tearing off a portion of the conductive layer 1. This can result in short-circuits or current leakages due to a crushing of the layers of the integrated circuit located under the contact pad. In addition, during its travel over the surface of the contact pad, the tip of the probe can encounter the passivating layer 2 and could therefore partially tear it off.
Now the role of the passivating layer is to protect the integrated circuit against corrosion and contamination risks. If this layer is partially torn off, the service life and the reliability of the integrated circuit can be affected.
FIG. 3 is a cross-section of an edge of an integrated circuit IC. In FIG. 3, the integrated circuit IC is produced in a wafer in a semi-conductive material 4. The active face of the wafer 4 is covered by a first electrically insulating layer 3b. A layer of a first metallization plane is formed on the electrically insulating layer 3b. The layer of the first metallization plane comprises an electrically conductive path 1b formed around the integrated circuit IC. Vias 6 cross the insulating layer 3b to connect the conductive path 1b to doped zones formed in the semi-conductive material 4. Another electrically insulating layer 3a is formed on the first metallization plane. A layer of a second metallization plane is formed on the layer 3a. The layer of the second metallization plane comprises an electrically conductive path 1a formed around the integrated circuit IC, above the conductive path 1b. Vias 5 cross the insulating layer 3b to connect the conductive path 1a of the second metallization plane to the conductive path 1b of the first metallization plane. The set of conductive paths 1a, 1b forms an edge ground line Zc formed around the integrated circuit. The ground line Zc forms an electrical and mechanical shield ring of the integrated circuit.
The integrated circuit may comprise more metallization planes. In this case, the ground line comprises one conductive path in each metallization plane.
A passivating layer 2 covers the entire integrated circuit except for an edge zone 8 on the edge of the integrated circuit IC. The edge zone 8 corresponds to the sawing zone or scribe line of the wafer to individualize the integrated circuits. The centre of the scribe line is indicated by the arrow 7.
Once the integrated circuits implanted onto the wafer are tested, the wafer is cut along the scribe lines into chips each comprising an integrated circuit. The width of the scribe lines is typically in the order of 80 to 100 μm. The integrated circuits are insulated from the scribe lines by the ground line Zc that is used as a protection against the risks of contamination and corrosion resulting from faults in the passivating layer 2 following the sawing of the wafer (entry of impurities into the integrated circuit through the cut edge).
The scribe lines are generally provided wide enough so that a sufficient distance remains after cutting between the edge ground line and the cut edge of the chip. However, the sawing operation can cause cracks in the semi-conductive material or in the passivating layer 2. These cracks affect the integrity of the edge ground line which can then no longer play its protective role. Therefore, these faults also affect the service life and the reliability of the integrated circuit.
Any damage caused by the probes during the electrical testing or during the sawing operation can be detected by an optical inspection. If this inspection is performed by operators, it is not reliable and is relatively expensive. This detection can also be done automatically by a pattern recognition system.
Whether it is done manually or automatically, this inspection is not done systematically particularly due to the fact that it requires considerable processing time. The result is that damaged integrated circuits can be delivered to customers.